Rangkaian Logika dengan bahasa VHDL,
contoh soal:
"Write the behavioral VHDL code for converting an 8-bit unsigned binary number to two 4-bit BCD numbers. These two BCD numbers represent the tenth and unit digits of a decimal number. Also, turn on the decimal point LED for the unit digit if the 8-bit binary number is in the one hundreds range, and turn on the decimal point LED for the tenth digit if the 8-bit binary number is in the two hundreds range. This circuit is used as the output circuit for many designs in later chapters."
Jawabannya :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following
library declaration if using
-- arithmetic functions with
Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following
library declaration if instantiating
-- any Xilinx primitives in this
code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Tugas2 is
Port (
number
: in std_logic_vector (7 downto
0);
hundreds : out std_logic_vector (6 downto
0);
tens
: out std_logic_vector (6 downto 0);
ones
: out std_logic_vector (6 downto 0)
);
end Tugas2;
architecture Behavioral of Tugas2
is
signal ratusan,puluhan,satuan :
STD_LOGIC_VECTOR (3 downto 0);
begin
bin_to_bcd : process (number)
-- Internal variable for storing bits
variable shift : unsigned(19 downto 0);
-- Alias for parts of shift register
alias num is shift(7 downto 0);
alias one is shift(11 downto 8);
alias ten is shift(15 downto 12);
alias hun is shift(19 downto 16);
begin
-- Clear previous number and store new
number in shift register
num := unsigned(number);
one := X"0";
ten := X"0";
hun := X"0";
-- Loop eight times
for i in 1 to num'Length loop
-- Check if any digit is greater than
or equal to 5
if one >= 5 then
one := one + 3;
end if;
if ten >= 5 then
ten := ten + 3;
end if;
if hun >= 5 then
hun := hun + 3;
end if;
-- Shift entire register left once
shift := shift_left(shift, 1);
end loop;
-- Push decimal numbers to output
ratusan <= std_logic_vector(hun);
puluhan <= std_logic_vector(ten);
satuan <= std_logic_vector(one);
end process;
PROCESS
(ratusan) --seven segmen 1
begin
case ratusan is
when
"0000"=> hundreds <="0000001"; -- '0'
when
"0001"=> hundreds <="1001111"; -- '1'
when
"0010"=> hundreds <="0010010"; -- '2'
when
"0011"=> hundreds <="0000110"; -- '3'
when
"0100"=> hundreds <="1001100"; -- '4'
when
"0101"=> hundreds <="0100100"; -- '5'
when
"0110"=> hundreds <="0100000"; -- '6'
when
"0111"=> hundreds <="0001111"; -- '7'
when
"1000"=> hundreds <="0000000"; -- '8'
when
"1001"=> hundreds <="0000100"; -- '9'
when
others=> hundreds <="1111111";
end
case;
end
process;
PROCESS
(puluhan) --seven segmen 2
begin
case puluhan is
when
"0000"=> tens <="0000001"; -- '0'
when
"0001"=> tens <="1001111"; -- '1'
when
"0010"=> tens <="0010010"; -- '2'
when
"0011"=> tens <="0000110"; -- '3'
when
"0100"=> tens <="1001100"; -- '4'
when
"0101"=> tens <="0100100"; -- '5'
when
"0110"=> tens <="0100000"; -- '6'
when
"0111"=> tens <="0001111"; -- '7'
when
"1000"=> tens <="0000000"; -- '8'
when
"1001"=> tens <="0000100"; -- '9'
when
others=> tens <="1111111";
end
case;
end
process;
PROCESS
(satuan) --seven segmen 3
begin
case satuan is
when
"0000"=> ones <="0000001"; -- '0'
when
"0001"=> ones <="1001111"; -- '1'
when
"0010"=> ones <="0010010"; -- '2'
when
"0011"=> ones <="0000110"; -- '3'
when
"0100"=> ones <="1001100"; -- '4'
when
"0101"=> ones <="0100100"; -- '5'
when
"0110"=> ones <="0100000"; -- '6'
when
"0111"=> ones <="0001111"; -- '7'
when
"1000"=> ones <="0000000"; -- '8'
when
"1001"=> ones <="0000100"; -- '9'
when
others=> ones <="1111111";
end
case;
end
process;
end Behavioral;
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