Kode VHDL Gerbang AND, NOT, NAND, NOR Gate

            Dibawah ini adalah contoh bahasa pemerograman VHDL rangkaian logika, yang terdiri dari komponen AND, NOT, NAND, dan OR. berikut adalah kode programnya:
( dapat dijalankan di modelsim atau Xilink ISE )

AND
library IEEE;
used IEEE.STD_LOGIC_1164.ALL;

ENTITY AND_Gate is
Port (I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
O : out STD_LOGIC);
end AND_Gate;

architecture Behavioral of AND_Gate is
begin
PROCESS(I0,I1)
BEGIN
O <= I0 AND I1;
END PROCESS;
end Behavioral;


NOT
entity NOT_Gate is
Port ( I0 : in STD_LOGIC;
O : out STD_LOGIC);
end NOT_Gate;

architecture Behavioral of NOT_Gate is

begin
PROCESS (I0)
BEGIN
O <= NOT I0;
END PROCESS;
end Behavioral;


NAND
entity NAND_Gate is
Port ( I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
O : out STD_LOGIC);
end NAND_Gate;

architecture Behavioral of NAND_Gate is

begin
PROCESS (I0,I1)
BEGIN
O <= I0 NAND I1;
END PROCESS;
end Behavioral;


NOR
entity NOR_Gate is
Port ( I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
O : out STD_LOGIC);
end NOR_Gate;

architecture Behavioral of NOR_Gate is

begin
PROCESS (I0,I1)
BEGIN
O <= I0 NOR I1;
END PROCESS;
end Behavioral;