VHDL Code Processor 8 Bit

In this post, I want to share VHDL Code Processor 8 Bit . I use software Xillink for coding this project. Enjoy guys :)

KOMPONEN MEMORY

1.       MUX 8 BIT

----------------------------------------------------------------------------------

-- Create Date:    16:55:25 05/18/2014

-- Design Name: Rizal Hidayat

-- Module Name:    mux8bit - Behavioral

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux8bit is

    Port ( a,b : in  std_logic_vector(7 downto 0);

           s : in  std_logic;

           o : out std_logic_vector (7 downto 0));

end mux8bit;

architecture Behavioral of mux8bit is

begin

process (a,b,s)

begin

if s = '0' then o <= a;

elsif s = '1' then o <= b;

end if;

end process;     

end Behavioral;

2.       ROM

----------------------------------------------------------------------------------

-- Create Date:    17:39:32 05/18/2014

-- Design Name:

-- Module Name:    ROM16X8 - Behavioral

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ROM16X8 is

    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0) :="0000";

           o : out  STD_LOGIC_VECTOR (7 downto 0));

end ROM16X8;

architecture Behavioral of ROM16X8 is

type ROM_ARR is array (0 TO 15)OF STD_LOGIC_VECTOR(7 DOWNTO 0);

signal mem : ROM_ARR:=(

"00001010","01001011","11000001","10001101",

"01101110","00111101","01001111","00111111",

"11111111","00000000","00000000","00000000",

"00000000","00000000","00000000","00000000");

begin

o <= mem ( conv_integer (a));

end Behavioral;

3.       RAM

----------------------------------------------------------------------------------

-- Create Date:    18:22:12 05/18/2014

-- Design Name:

-- Module Name:    ram16x8 - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.all;   

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity ram16x8 is

     port(

         clk : in STD_LOGIC;

         we : in STD_LOGIC;

         alamat : in STD_LOGIC_VECTOR(3 downto 0);

         a : in STD_LOGIC_VECTOR(7 downto 0);

         dout : out STD_LOGIC_VECTOR(7 downto 0)

         );

end ram16x8;

architecture Behavioral of ram16x8 is      

type memory is array (0 to 15) of std_logic_vector (7 downto 0);   

signal mem : memory;

begin

process (clk,we)

begin

if we = '1' and clk' event and clk = '1' then mem(conv_integer(alamat)) <= a;

elsif we = '0' and clk' event and clk = '1' then dout <= mem (conv_integer (alamat));

end if;

end process;

end Behavioral;

MEMORY

----------------------------------------------------------------------------------

-- Create Date:    20:55:27 05/19/2014

-- Design Name:

-- Module Name:    memory - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity memory is

    Port ( a2 : in  STD_LOGIC_VECTOR (3 downto 0);

           b2 : in  STD_LOGIC;

                                                  c2 : in  STD_LOGIC;

                                                  d2 : in  STD_LOGIC;

                                                  e2 : in  STD_LOGIC_VECTOR (7 downto 0);

                                                  o : out STD_LOGIC_VECTOR (7 downto 0));

end memory;

architecture Behavioral of memory is

component mux8bit is

Port (   a,b : in  STD_LOGIC_VECTOR (7 downto 0);

           s : in  STD_LOGIC;

           o : out  STD_LOGIC_VECTOR (7 downto 0));

end component;

component ROM16x8 is

Port ( a : in  STD_LOGIC_VECTOR (3 downto 0) := "0000";

           o : out  STD_LOGIC_VECTOR (7 downto 0));

end component;

component ram16x8 is

Port (   clk : in STD_LOGIC;

         we : in STD_LOGIC;

         alamat : in STD_LOGIC_VECTOR(3 downto 0);

         a : in STD_LOGIC_VECTOR(7 downto 0);

         dout : out STD_LOGIC_VECTOR(7 downto 0)

                                                );

end component;

signal x11,x10 : STD_LOGIC_VECTOR (7 downto 0);--8bit

signal x16,x17 : STD_LOGIC;--1bit

begin

--x10,x11,x17

mux8a : mux8bit

port map( a => x10, b => x11, o => o, s => d2 );

rom : ROM16x8

port map ( a => a2, o=>x10);

ram : ram16x8

port map ( a => e2, alamat => a2, clk=>b2, we=> x17, dout=>x11);

x17 <= c2 AND d2;

end Behavioral;

DATAPATH

1.       REGISTER 8 BIT

----------------------------------------------------------------------------------

-- Create Date:    18:05:43 05/18/2014

-- Design Name:

-- Module Name:    register8bit - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity register8bit is

    Port (   

     a   : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

    en  : IN STD_LOGIC; -- load/enable.

    clr : IN STD_LOGIC; -- clear.

    clk : IN STD_LOGIC; -- clock.

    o   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

end register8bit;

architecture Behavioral of register8bit is

signal x:std_logic_vector (7 downto 0);

begin

    process(clk, clr)

      begin

        if clr = '1' then

            x<= "00000000";

        elsif en = '1' and clk' event and clk = '1' then x <= a ;

end if;

o <= x;

    end process;

end Behavioral;

2.       REGISTER 5 BIT

----------------------------------------------------------------------------------

-- Create Date:    18:05:43 05/18/2014

-- Design Name:

-- Module Name:    register5bit - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity register5bit is

    Port (  a   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);

    en  : IN STD_LOGIC; -- load/enable.

    clr : IN STD_LOGIC; -- clear.

    clk : IN STD_LOGIC; -- clock.

    o   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));

end register5bit;

architecture Behavioral of register5bit is

begin

    process(clk, clr,en)

      begin

        if clr = '1' then

            o <= "00000";

        elsif (rising_edge(clk)) then

            if en = '1' then

                o <= a;

            end if;

        end if;

    end process;

end Behavioral;

3.       MULTIPLEXIER 5 BIT

----------------------------------------------------------------------------------

-- Create Date:    16:44:50 05/18/2014

-- Design Name:

-- Module Name:    mux5bit - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux5bit is

    Port ( a,b : in  std_logic_vector(4 downto 0);

           s : in  std_logic;

           o : out std_logic_vector (4 downto 0));

end mux5bit;

architecture Behavioral of mux5bit is

begin

process (a,b,s)

begin

if s = '0' then o <= a;

elsif s = '1' then o <= b;

end if;

end process;     

end Behavioral;

4.       MULTIPLEXIER 8 BIT

----------------------------------------------------------------------------------

-- Create Date:    16:55:25 05/18/2014

-- Design Name:

-- Module Name:    mux8bit - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux8bit is

    Port ( a,b : in  std_logic_vector(7 downto 0);

           s : in  std_logic;

           o : out std_logic_vector (7 downto 0));

end mux8bit;

architecture Behavioral of mux8bit is

begin

process (a,b,s)

begin

if s = '0' then o <= a;

elsif s = '1' then o <= b;

end if;

end process;     

end Behavioral;

5.       ALU 8 BIT

----------------------------------------------------------------------------------

-- Create Date:    17:09:33 05/18/2014

-- Design Name:

-- Module Name:    alu8bit - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu8bit is

Port ( a,b : in  STD_LOGIC_VECTOR (7 downto 0);

           s : in  STD_LOGIC_VECTOR (1 downto 0);

           o : out  STD_LOGIC_VECTOR (7 downto 0));

end alu8bit;

architecture Behavioral of alu8bit is

begin

process (a,b,s)

begin

if s = "00" then o <= a + b;

elsif s = "01" then o <= a - b;

elsif s = "10" then o <= a nand b;

elsif s = "11" then o <= a nor b;

end if;

end process;

end Behavioral;

6.       DATAPATH CODE

----------------------------------------------------------------------------------

-- Create Date:    13:35:22 05/19/2014

-- Design Name:

-- Module Name:    datapatch - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

entity datapatch is

port (     IRload : in std_logic;

PCload : in std_logic;

Aload : in std_logic;

Asel : in std_logic;

ALUsel : in std_logic_vector( 1 downto 0);

JPMux : in std_logic;

Meminst : in std_logic;

Clock : in std_logic;

Reset : in std_logic;

IR : out std_logic_vector ( 7 downto 5 );

Aeq0 : out std_logic;

MQ70 : in STD_LOGIC_VECTOR (7 downto 0);

MD70 : out STD_LOGIC_VECTOR (7 downto 0);

MAdd40 : out STD_LOGIC_VECTOR (4 downto 0)

);

end datapatch;

architecture Behavioral of datapatch is

component alu8bit is

Port ( a,b : in  std_logic_vector(7 downto 0);

           s : in  std_logic_vector(1 downto 0);

           o : out std_logic_vector (7 downto 0));

end component;

component mux5bit is

Port ( a,b : in  std_logic_vector(4 downto 0);

           s : in  std_logic;

           o : out std_logic_vector (4 downto 0));

end component;

component mux8bit is

Port ( a,b : in  std_logic_vector(7 downto 0);

           s : in  std_logic;

           o : out std_logic_vector (7 downto 0));

end component;

component register5bit is

Port (   

                 a   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);

                en  : IN STD_LOGIC; -- load/enable.

                clr : IN STD_LOGIC; -- clear.

                clk : IN STD_LOGIC; -- clock.

                o   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));

end component;

component register8bit is

Port (   

                 a   : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

                en  : IN STD_LOGIC; -- load/enable.

                clr : IN STD_LOGIC; -- clear.

                clk : IN STD_LOGIC; -- clock.

                o   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

end component;

--component ram16x8 is

--Port(

--         clk : in STD_LOGIC;

--         we : in STD_LOGIC;

--         alamat : in STD_LOGIC_VECTOR(3 downto 0);

--         a : in STD_LOGIC_VECTOR(7 downto 0);

--         dout : out STD_LOGIC_VECTOR(7 downto 0)

--         );

--end component;

--component ROM16x8 is

 --   Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);

 --          o : out  STD_LOGIC_VECTOR (7 downto 0));

--end component;

signal x1,x2,x3,x4,x5,x11,x10 : STD_LOGIC_VECTOR (7 downto 0);--8bit

signal x7,x8,x14,x9 : STD_LOGIC_VECTOR (4 downto 0);--5bit

signal x6 : STD_LOGIC_VECTOR( 7 downto 5 );--3bit

--signal x15 : STD_LOGIC_VECTOR (3 downto 0);--4bit

--signal x16,x17 : STD_LOGIC;--1bit

begin

regist8_a : register8bit

port map(

a => x1, clk =>Clock, clr => Reset, en => IRload, o=>x5);

regist8_b : register8bit

port map(a => x4, clk =>Clock, clr => Reset, en => Aload, o=>x3);

regist5_a : register5bit

port map(

a => x14 ,clr => Reset, clk => Clock, en => PCLoad, o=> x9);

mux5_a : mux5bit

port map(a => x8, b => x7, s => JPMux, o=>x14);

mux5_b : mux5bit

port map(a => x9, b=> x7, s => Meminst, o=>MAdd40 );

--mux8a : mux8bit

--port map(

--a => x10, b=>x11, s => x16, o=>x1);

--rom : ROM16x8

--port map ( a => x15, o=>x10);

--ram : ram16x8

--port map ( a => x3, alamat=>x15, clk=>Clock, we=>x17, dout=>x11);

mux8_b : mux8bit

port map (a => x2, b=> x1, s => Asel, o=>x4 );

alu8 : alu8bit

port map (a => x3, b => x1, o=> x2, s => ALUsel);

x6 <= x5( 7 downto 5);

x7 <= x5 ( 4 downto 0);

x8 <= x9 + 1;

Aeq0 <= not (x3(7) or x3(6) or x3(5) or x3(4) or x3(3) or x3(2) or x3(1) or x3(0));

x1 <= MQ70;

MD70 <= x3;

end Behavioral;

CONTROL UNIT

----------------------------------------------------------------------------------

-- Create Date:    22:14:55 05/19/2014

-- Design Name:

-- Module Name:    ControlUnit - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ControlUnit is

port (     IR : in  STD_LOGIC_VECTOR (7 downto 5);

           Aeq0 : in  STD_LOGIC;

                                                  Clock : in STD_LOGIC;

                                                  Reset : in STD_LOGIC;

                                                  IRLoad : out STD_LOGIC;

                                                  PCLoad : out STD_LOGIC;

                                                  ALoad : out STD_LOGIC;

                                                  Asel : out STD_LOGIC;

                                                  ALUsel : out STD_LOGIC_VECTOR (1 downto 0);

                                                  JPMux : out STD_LOGIC;

                                                  Meminst : out STD_LOGIC;

                                                  MemWr : out STD_LOGIC;

                                                  Halt : out STD_LOGIC);

end ControlUnit;

architecture Behavioral of ControlUnit is

type state is (start,fetch,decode,load,store,add,sub,nd,nr,jz,stop);

signal nexst,prest : state;

begin

aduh:process (Reset,Clock)

begin

case prest is

                when start => IRLoad <= '0'; JPMux <= '0'; PCLoad <= '0'; Meminst <='0'; MemWr <= '0'; Asel <= '0'; ALoad <= '0'; Halt <= '0'; nexst <= fetch;

                when fetch => IRLoad <= '1'; JPMux <= '0'; PCLoad <= '1'; Meminst <='0'; MemWr <= '0'; Asel <= '0'; ALoad <= '0'; Halt <= '0'; nexst <= decode;

                when decode => IRLoad <= '0'; JPMux <= '0'; PCLoad <= '0'; Meminst <='1'; MemWr <= '0'; Asel <= '0'; ALoad <= '0'; Halt <= '0';

                case IR is             

                                when "000" => nexst <= load;

                                when "001" => nexst <= store;

                                when "010" => nexst <= add;

                                when "011" => nexst <= sub;

                                when "100" => nexst <= nd;

                                when "101" => nexst <= nr;

                                when "110" => nexst <= jz;

                                when others => null;

                end case;

                when load => IRLoad <= '0'; JPMux <= '0'; PCLoad <= '0'; Meminst <= '0'; MemWr <= '0'; Asel <= '1'; ALoad <= '1'; Halt <= '0'; nexst <= start;

                when store => IRLoad <= '0'; JPMux <= '0'; PCLoad <= '0'; Meminst <= '1'; MemWr <= '1'; Asel <= '0'; ALoad <= '0'; Halt <= '0'; nexst <= start;

                when add => IRLoad <= '0'; JPMux <= '0'; PCLoad <= '0'; Meminst <= '0'; MemWr <= '0'; Asel <= '0'; ALoad <= '1'; ALUsel <= "00"; Halt <= '0'; nexst <= start;

                when sub => IRLoad <= '0'; JPMux <= '0'; PCLoad <= '0'; Meminst <= '0'; MemWr <= '0'; Asel <= '0'; ALoad <= '1'; ALUsel <= "01"; Halt <= '0'; nexst <= start;

                when nd => IRLoad <= '0'; JPMux <= '0'; PCLoad <= '0'; Meminst <= '0'; MemWr <= '0'; Asel <= '0'; ALoad <= '1'; ALUsel <= "10"; Halt <= '0'; nexst <= start;

                when nr => IRLoad <= '0'; JPMux <= '0'; PCLoad <= '0'; Meminst <= '0'; MemWr <= '0'; Asel <= '0'; ALoad <= '1'; ALUsel <= "11"; Halt <= '0'; nexst <= start;

                when jz => IRLoad <= '0'; JPMux <= '1'; PCLoad <= Aeq0; Meminst <= '0'; MemWr <= '0'; Asel <= '0'; ALoad <= '0'; Halt <= '0'; nexst <= start;

                when stop => IRLoad <= '0'; JPMux <= '0'; PCLoad <= '0'; Meminst <= '0'; MemWr <= '0'; Asel <= '0'; ALoad <= '0'; Halt <= '1'; nexst <= start;

end case;

end process;

process (Clock,Reset)

begin

if reset = '1' then

prest <= start;

elsif Clock' event and Clock = '1' then

prest <= nexst;

end if;

end process;

end Behavioral;

PROCESSOR

----------------------------------------------------------------------------------

-- Create Date:    22:19:40 05/19/2014

-- Design Name:

-- Module Name:    Processor - Behavioral

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Processor is

Port (     MDD70                 : out std_logic_vector(7 downto 0);

                MDQ70                 : in  std_logic_vector(7 downto 0);

                MAdd                   : out std_logic_vector(4 downto 0);

                MemWr               : out std_logic;

                Halt                        : out std_logic;

                Clk_processor   : in  std_logic;

                Reset_processor : in  std_logic);

end Processor;

architecture Behavioral of Processor is

component datapatch is

Port (

                                IRload                   : in std_logic;

                                PCload                 : in std_logic;

                                Aload                    : in std_logic;

                                Asel                       : in std_logic;

                                ALUsel                 : in std_logic_vector ( 1 downto 0);

                                JPMux                 : in std_logic;

                                Meminst              : in std_logic;

                                Clock                     : in std_logic;

                                Reset                    : in std_logic;

                                IR                            : out std_logic_vector ( 7 downto 5 );

                                Aeq0                     : out std_logic;

                                MQ70                    : in std_logic_vector (7 downto 0);

                                MD70                    : out std_logic_vector (7 downto 0);

                                MAdd40               : out std_logic_vector (4 downto 0));

                                end component;

component ControlUnit is

Port (                     IR                            : in  std_logic_vector (7 downto 5);

                                Aeq0                     : in  std_logic;

                                                  Clock   : in std_logic;

                                                  Reset : in std_logic;

                                                  IRLoad : out std_logic;

                                                  PCLoad : out std_logic;

                                                  ALoad : out std_logic;

                                                  Asel     : out std_logic;

                                                  ALUsel : out std_logic_vector (1 downto 0);

                                                  JPMux                : out std_logic;

                                                  Meminst: out std_logic;

                                                  MemWr             : out std_logic;

                                                  Halt      : out std_logic);                                  

end component;

signal a : STD_LOGIC_VECTOR (7 downto 5);--IR

signal b, c, d, e, f, h, i : STD_LOGIC;

signal g : STD_LOGIC_VECTOR (1 downto 0);--ALUsel

begin

DATAPATCH_2 : datapatch

port map ( IR => a, Aeq0 => b, IRLoad => c, PCLoad => d, ALoad => e, Asel => f, ALUsel => g, JPMux => h, Meminst => i,Clock => Clk_processor, Reset => Reset_processor, MQ70 => MDQ70, MD70 => MDD70, MAdd40 => MAdd);

CONTROL_UNIT : ControlUnit

port map ( IR => a, Aeq0 => b , IRLoad => c, PCLoad => d, ALoad => e, Asel => f, ALUsel => g, JPMux => h, Meminst => i,Clock => Clk_processor, Reset => Reset_processor);

end Behavioral;